TNETX3100 datasheet(39/80 Pages) TI1

39 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DRAM test-access operation

(continued)

• Clear the forward pointer, flag and perform a DRAM read:

DIO write (address 00D4) = 00

;Forward pointer least-significant bit

DIO write (address 00D5) = 00

;Forward pointer

DIO write (address 00D6) = 00

;Forward pointer

DIO write (address 00D7) = 00

;Forward pointer most-significant bit

DIO write (address 00D8) = x0

;Flag

DIO write (address 00D9) = 00

;DRAM address least-significant bit

DIO write (address 00DA) = 00

;DRAM address

DIO write (address 00DB) = 00

;DRAM address most-significant bit

• Now wait for the read from DRAM to complete by polling the DRAMACT bit within the DRAM flag

DIO read (address 00D8) = 8x

DMA transfer not complete

DIO read (address 00D8) = 0x

DMA transfer complete

• Read the forward pointer, flag, and DRAM data:

DIO read (address 00D4–00D7)

DIO read (address C0D8)

DIO read [address C000 + (10 * n)] through [address C008 + (10 * n)]

where n = 0–7

DIATST register at 0x00DD

BIT

Reserved

DPWRAP

INTWRAP

Reserved

Initial Values After Reset

BIT

NAME

FUNCTION

7–4

Reserved

DPWRAP

Duplex wrap mode. When DPWRAP = 1, all ports are forced into full-duplex mode and all ports can receive

frames they transmit. This enables external wrap testing at the PHY. When DPWRAP = 0, all ports function

normally.

2–1

INTWRAP

Internal wrap mode. Ports 01–09 internally wrap back according to the following two-bit coding (INTWRAP

bit 2 and bit 1, respectively):

00 No internal wrapping

01 All ports internally wrapped except port 00 (uplink)

10 All ports internally wrapped except port 02

11 All ports internally wrapped except port 09

The port that is not wrapped (00, 02, or 09) should be used to inject and observe test data frames from

the internally wrapped ports.

Reserved

Reserved. Should always be written as a 0.

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