HD6417618A datasheet(320/646 Pages) RENESAS

320 / 646 page

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 288 of 610

REJ09B0131-0600

(a)

Receive Descriptor 0 (RD0)

RD0 indicates the receive frame status. The CPU and E-DMAC use RD0 to report the frame

receive status.

Bit

Bit Name

Initial

value

R/W

Description

RACT

R/W

Receive Descriptor Active

Indicates that this descriptor is active. The E-DMAC

resets this bit after receive data has been transferred

to the receive buffer. On completion of receive frame

processing, the CPU sets this bit to prepare for

reception.

0: The receive descriptor is invalid.

Indicates that the receive buffer is not ready

(access disabled by E-DMAC), or this bit has been

reset by a write-back operation on termination of

E-DMAC frame transfer processing (completion or

suspension of reception).

If this state is recognized in an E-DMAC descriptor

read, the E-DMAC terminates receive processing

and receive operations cannot be continued.

Reception can be restarted by setting RACT to 1

and executing receive initiation.

1: The receive descriptor is valid

Indicates that the receive buffer is ready (access

enabled) and processing for frame transfer from

the FIFO has not been executed, or that frame

transfer is in progress.

When this state is recognized in an E-DMAC

descriptor read, the E-DMAC continues with the

receive operation.

RDLE

R/W

Receive Descriptor List Last

After completion of the corresponding buffer transfer,

the E-DMAC references the first receive descriptor.

This specification is used to set a ring configuration

for the receive descriptors.

0: This is not the last receive descriptor list

1: This is the last receive descriptor list

HD6417618A Datasheet(PDF) 320 Page - Renesas Technology Corp

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