R8CSLASH20 datasheet(307/501 Pages) RENESAS

307 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 291 of 458

REJ09B0250-0200

Figure 16.8

Registers SSTDR and SSRDR

Figure 16.9

PMR Register

SS Transmit Data Register

Symbol

Address

After Reset

SSTDR

00BEh

FFh

Function

Store the transmit data.

The stored transmit data is transferred to the SSTRSR register and the transmit is started

w hen detecting the SSTRSR register is empty.

When the next transmit data is w ritten to the SSTDR register during the data transmit from the

SSTRSR register, the data can be transmitted continuously.(1)

When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in

w hich MSB and LSB are reversed can be read, after w riting to the SSTDR register.

SS Receive Data Register

Symbol

Address

After Reset

SSRDR

00BFh

FFh

NOTE:

1. The SSRDR register maintains the receive data before the overrun error occurs w hen the ORER bit in the SSSR

therefore, should be discarded.

Store the receive data.(1)

The receive data is transferred to the SSRDR register and the receive operation is completed

w hen receiving 1-byte data to the SSTRSR register. At this time, the follow ing receive is

possible. The continuous receive is possible by the SSTRSR and SSRDR registers.

Function

Port Mode Register

Symbol

Address

After Reset

PMR

00F8h

00h

Bit Symbol

Bit Name

Function

IICSEL

0 : SSU function selects

1 : I2C bus function selects

Set to 0

0 : I/O port P6_6, P6_7

1 : TXD1, RXD1

Set to 0

—

Reserved bits

SSU/I2C bus sw itch bit

—

Reserved bits

U1PINSEL

Port TXD1/RXD1 sw itch bit

—

(b3-b0)

—

(b6-b5)

b3 b2

b7 b6 b5 b4

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