R8CSLASH20 datasheet(310/501 Pages) RENESAS

310 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 294 of 458

REJ09B0250-0200

16.2.2

SS Shift Register (SSTRSR)

The SSTRSR register is the shift register to transmit and receive the serial data.

When the transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the

SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to the bit 0 in the SSTRSR

SSTRSR register.

16.2.2.1

Association between Data I/O Pins and SS Shift Register

Connecting association between the data I/O pin and SSTRSR register (SS shift register) changes according to

a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. Also,

connecting association changes according to the BIDE bit in the SSMR2 register.

Figure 16.11 shows an Association between Data I/O Pins and SSTRSR Register.

Figure 16.11

Association between Data I/O Pins and SSTRSR Register

SSTRSR Register

SSO

SSI

• When SSUMS bit = 0

(clock synchronous communication mode)

SSTRSR Register

SSO

SSI

• When SSUMS bit = 1 (4-wire bus communication

mode), BIDE bit = 0 (standard mode) and MSS bit = 0

(operates as slave device)

SSTRSR Register

SSO

SSI

• When SSUMS bit = 1 (4-wire bus communication mode),

BIDE bit = 0 (standard mode) and MSS bit = 1 (operates

as master device)

SSTRSR Register

SSO

SSI

• When SSUMS bit = 1 (4-wire bus communication mode),

BIDE bit = 1 (bidirectional mode)

R8C/20 Datasheet(PDF) 310 Page - Renesas Technology Corp