R8CSLASH20 datasheet(311/501 Pages) RENESAS

311 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 295 of 458

REJ09B0250-0200

16.2.3

Interrupt Requests

Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end,

receive data full, overrun error and conflict error. Since these interrupt requests are assigned to the clock

synchronous serial I/O with chip select interrupt vector table, determining interrupt sources by flags is required.

Table 16.3 shows the Clock Synchronous Serial I/O with Chip Select Interrupt Requests.

CEIE, RIE, TEIE and TIE: Bits in SSER register

ORER, RDRF, TEND and TDRE: Bits in SSSR register

Generation conditions of Table 16.3 are met, a clock synchronous serial I/O with chip select interrupt request is

generated. Set the each interrupt source to 0 by a clock synchronous serial I/O with chip select interrupt routine.

However, the TDRE and TEND bits are automatically set to 0 by writing the transmit data to the SSTDR

data to the SSTDR register, at the same time the TDRE bit is set to 1 (data is transmitted from the SSTDR to

SSTRSR registers) again and when setting the TDRE bit to 0 (data is not transmitted from the SSTDR to

SSTRSR registers), additional 1-byte data may be transmitted.

Table 16.3

Clock Synchronous Serial I/O with Chip Select Interrupt Requests

Interrupt Request

Abbreviation

Generation Condition

Transmit Data Empty

TXI

TIE = 1, TDRE = 1

Transmit End

TEI

TEIE = 1, TEND = 1

Receive Data Full

RXI

RIE = 1, RDRF = 1

Overrun Error

OEI

RIE = 1, ORER = 1

Conflict Error

CEI

CEIE = 1, CE = 1

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