R8CSLASH20 datasheet(73/501 Pages) RENESAS

73 / 501 page

R8C/20 Group, R8C/21 Group

7. Programmable I/O Ports

Rev.2.00 Aug 27, 2008

Page 57 of 458

REJ09B0250-0200

X: 0 or 1

NOTES:

Pulled up by setting the PU07 bit in the PUR0 register to 1.

N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.

X: 0 or 1

NOTES:

Pulled up by setting the PU07 bit in the PUR0 register to 1.

N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.

X: 0 or 1

NOTE:

Pulled up by setting the PU07 bit in the PUR0 register to 1.

Table 7.31

Port P3_4/SDA/SCS

PD3

SSMR2

PMR

ICCR1

Function

Bit

PD3_4

CSS1

CSS0

IICSEL

ICE

Setting

value

Input port(1)

Output port(2)

SCS input

SCS output(2)

SDA input/output

Table 7.32

Port P3_5/SCL/SSCK

PD3

Clock Synchronous Serial I/O with Chip Select

(Refer to Table 16.4 Association between

Communication Modes and I/O Pins.)

PMR

ICCR1

Function

Bit

PD3_5

SSCK output control

SSCK input control

IICSEL

ICE

Setting

value

Input port(1)

Output port(2)

SSCK input

SSCK output(2)

SCL input/output

Table 7.33

Port P3_7/SSO

PD3

Clock Synchronous Serial I/O with Chip Select

(Refer to Table 16.4 Association between

Communication Modes and I/O Pins.)

SSMR2

PMR

Function

Bit

PD3_7

SSO output control

SSO input control

SOOS

IICSEL

Setting

value

Input port(1)

Output port

SSO input

SSO output (CMOS output)

SSO output (N-channel open-drain

output)

Table 7.34

Port P4_2/VREF

ADCON1

Function

Bit

VCUT

Setting

value

Input port

Input port/VREF input

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