R8CSLASH20 datasheet(339/501 Pages) RENESAS

339 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 323 of 458

REJ09B0250-0200

16.3.2

Interrupt Requests

The interrupt request of the I2C bus interface contains 6 types when the I2C bus format is used and 4 types when

the clock synchronous serial format is used.

Table 16.7 lists the Interrupt Requests of I2C Bus Interface.

Since these interrupt requests are allocated at the I2C bus interface interrupt vector table, determining the source

by each bit is necessary.

STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register

AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register

When the generation conditions on the Table 16.7 are met, the I2C bus interface interrupt request is generated.

Set the interrupt generation conditions to 0 by the I2C bus interface interrupt routine. However, the TDRE and

TEND bits are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is

automatically set to 0 by reading the ICDRR register. When writing transmit data to the ICDRT register, the

TDRE bit is set to 0. When data is transferred from the ICDRT to ICDRS registers, the TDRE bit is set to 1 and

when further setting the TDRE bit to 0, extra 1 byte may be transmitted.

Also, set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0.

Table 16.7

Interrupt Requests of I2C Bus Interface

Interrupt Request

Generation Condition

Format

I2C bus

Clock

Synchronous

Serial

Transmit Data Empty

TXI

TIE = 1 and TDRE = 1

Enabled

Transmit Ends

TEI

TEIE = 1 and TEND = 1

Enabled

Receive Data Full

RXI

RIE = 1 and RDRF = 1

Enabled

Stop Condition Detection

STPI

STIE = 1 and STOP = 1

Enabled

Disabled

NACK Detection

NAKI

NAKIE = 1 and AL = 1 (or

NAKIE = 1 and NACKF = 1)

Enabled

Disabled

Arbitration Lost / Overrun Error

Enabled

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