R8CSLASH20 datasheet(341/501 Pages) RENESAS

341 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 325 of 458

REJ09B0250-0200

16.3.3.2

Master Transmit Operation

In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an

acknowledge signal.

Figure 16.33 and Figure 16.34 show the Operation Timing in Master Transmit Mode (I2C Bus Interface Mode).

The transmit procedure and operation in master transmit mode are shown below.

(1) Set the STOP bit in the ICSR register to 0 to reset it. And then set the ICE bit in the ICCR1 register to 1

(transfer operation enabled). Set the WAIT and MLS bits in the ICMR register and set the CKS0 to

CKS3 bits in the ICCR1 register (initial setting).

(2) Read the BBSY bit in the ICCR2 register to confirm that the bus is free. Set the TRS and MST bits in

the ICCR1 register to master transmit mode. The start condition is generated by writing 1 to the BBSY

bit and 0 to the SCP bit by the MOV instruction.

(3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from the ICDRT

to ICDRS registers), write transmit data to the ICDRT register (data in which a slave address and R/W

are shown at the 1st byte). At this time, the TDRE bit is automatically set to 0 and data is transferred

from the ICDRT to ICDRS registers, the TDRE bit is set to 1 again.

(4) When the transmit of 1-byte data is completed while the TDRE bit is set to 1, the TEND bit in the ICSR

and confirm that the slave is selected. Write the 2nd-byte data to the ICDRT register. Since the slave

device is not acknowledged when the ACKBR bit is set to 1, generate the stop condition. The stop

condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV instruction.

The SCL signal is held “L” until data is available and the stop condition is generated.

(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1.

(6) When writing the number of bytes to be transmitted to the ICDRT register, wait until the TEND bit is

set to 1 while the TDRE bit is set to 1. Or wait for NACK (the NACKF bit in the ICSR register is set to

1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive

acknowledge bit is set to 1, transfer is halted). And generate the stop condition before setting the TEND

and NACKF bits to 0.

(7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.

R8C/20 Datasheet(PDF) 341 Page - Renesas Technology Corp