R8CSLASH20 datasheet(342/501 Pages) RENESAS

342 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 326 of 458

REJ09B0250-0200

Figure 16.33

Operating Timing in Master Transmit Mode (I2C Bus Interface Mode) (1)

Figure 16.34

Operating Timing in Master Transmit Mode (I2C Bus Interface Mode) (2)

SDA

(master output)

SCL

(master output)

SDA

(slave output)

TDRE bit in

ICSR register

TEND bit in

ICSR register

ICDRT register

ICDRS register

R/W

Slave address

Address + R/W

Processing

by program

(2) Instruction of

start condition

generation

(3) Data write to ICDRT

(4) Data write to ICDRT

(5) Data write to ICDRT

Data 2

Address + R/W

Data 1

SDA

(master output)

SCL

(master output)

SDA

(slave output)

TDRE bit in

ICSR register

TEND bit in

ICSR register

ICDRT register

ICDRS register

Data n

Processing

by program

(6) Generate stop condition and

set TEND bit to 0

(3) Data write to ICDRT

A/A

(7) Set to slave receive mode

Data n

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