R8CSLASH20 datasheet(340/501 Pages) RENESAS

340 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 324 of 458

REJ09B0250-0200

16.3.3

I2C Bus Interface Mode

16.3.3.1

I2C Bus Format

Setting the FS bit in the SAR register to 0 communicates in I2C bus format.

Figure 16.32 shows the I2C Bus Format and Bus Timing. The 1st frame following start condition consists of 8

bits.

Figure 16.32

I2C Bus Format and Bus Timing

SDA

SCL

SLA

R/W

DATA

1 to 7

(2) I2C bus timing

Explanation of symbols

: Start condition

The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.

SLA

: Slave address

R/W

: Indicates the direction of data transmit/receive

Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when

R/W value is 0.

: Acknowledge

The receive device sets the SDA signal to “L”.

DATA : Transmit / receive data

: Stop condition

The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.

R/W

DATA

A/A

(a) I2C bus format (FS = 0)

Transfer bit numbers (n = 1 to 8)

Transfer frame numbers (m = from 1)

R/W

DATA

A/A

(b) I2C bus format (when start condition is retransmitted, FS = 0)

Upper: Transfer bit numbers (n1, n2 = 1 to 8)

Lower: Transfer frame numbers (m1, m2 = from 1 )

SLA

A/A

R/W

DATA

SLA

(1) I2C bus Format

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