R8CSLASH20 datasheet(346/501 Pages) RENESAS

346 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 330 of 458

REJ09B0250-0200

16.3.3.4

Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive

clock and returns an acknowledge signal.

Figure 16.37 and Figure 16.38 show the Operation Timing in Slave Transmit Mode (I2C Bus Interface Mode).

The transmit procedure and operation in slave transmit mode are shown below.

(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set the WAIT and MLS bits in

the ICMR register and CKS0 to CKS3 bits in the ICCR1 register (initial setting). Set the TRS and MST

bits in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.

(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device

outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock.

At this time, if the 8-bit data (R/W) is set to 1, the TRS and TDRE bit in the ICSR register are set to 1,

the mode is switched to slave transmit mode automatically. When writing transmit data to the ICDRT

(3) When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT

TEND bit is set to 1, set the TEND bit to 0.

(4) The SCL signal is released by setting the TRS bit to 0 and performing the dummy-read of the ICDRR

(5) Set the TDRE bit to 0.

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