AS7150 datasheet(121/159 Pages) AMSOSRAM

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AS7150

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DS001130 • v3-00 • 2026-Jan-26

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8.11

Sequencer down sampler configuration

8.11.1

SEQ1_SINC_CFGA register (Address 0x61)

Table 90: SEQ1_SINC_CFGA register

Addr: 0x61

SEQ1_SINC_CFGA

Bit

Bit name

Default

Access

Bit description

7:5

seq1_sinc_ovs

R/W

This register controls the ADC oversampling

filter of sequencer 1 whose input signal is

the decimation filter output of the ADC

modulator. Please refer to Figure 17 which

provides an overview of the signal

processing flow including the oversampling

filter. The oversampling ratio is calculated

with the numerical register value of

seq1_sinc_ovs register to the power of two.

Please find the calculation formula below:

�� = 2

��1_��_��

4:2

seq1_sinc_dec

R/W

This register controls the ADC decimation

ratio of sequencer 1 which is applicable for

both ADC modulators. Please refer to

Figure 17 which provides an overview of the

signal processing flow including the

decimation filters.

0: Decimation factor 16

1: Decimation factor 32

2: Decimation factor 64

3: Decimation factor 128

4: Decimation factor 256

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