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CS8412 Datasheet(PDF) 21 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 21 Page - Cirrus Logic |
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21 / 38 page  CS8411 CS8412 DS61F1 21 FSYNC - Frame Sync, PIN 11. Delineates the serial data and may indicate the particular channel, left or right. Also, FSYNC may be configured as an input or output. The format is based on bits in control register 2. SDATA - Serial Data, PIN 26. Audio data serial output pin. ERF - Error Flag, PIN 25. Signals that an error has occurred while receiving the audio sample currently being read from the serial port. The errors that cause ERF to go high are enumerated in status register 2 and enabled by setting the corresponding bit in IEnable register 2. A4/FCK - Address Bus Bit 4/Frequency Clock, PIN 13. This pin has a dual function and is controlled by the FCEN bit in control register 1. A4 is the address bus pin as defined below. When used as FCK, an internal frequency comparator compares a 6.144 MHz clock input on this pin to the received clock frequency and stores the value in status register 1 as three FREQ bits. These bits indicate the incoming frequency as well as the tolerance. When defined as FCK, A4 is internally set to 0. Parallel Interface CS - Chip Select, PIN 24. This input is active low and allows access to the 32 bytes of internal memory. The address bus and RD/WR must be valid while CS is low. RD/WR - Read/Write, PIN 23. If RD/WR is low when CS goes active (low), the data on the data bus is written to internal memory. If RD/WR is high when CS goes active, the data in the internal memory is placed on the data bus. A4-A0 - Address Bus, PINS 13, 15-18. Parallel port address bus that selects the internal memory location to be read from or written to. Note that A4 is the dual function pin A4/FCK as described above. D0-D7 - Data Bus, PINS 27-28, 1-6. Parallel port data bus used to check status, read or write control words, or read internal buffer memory. INT - Interrupt, PIN 14. Open drain output that can signal the state of the internal buffer memory as well as error information. A 5k Ω resistor to VD+ is typically used to support logic gates. All bits affecting INT are maskable to allow total control over the interrupt mechanism. |
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