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CS8412 Datasheet(PDF) 19 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 19 Page - Cirrus Logic |
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19 / 38 page  CS8411 CS8412 DS61F1 19 Buffer Updates and Interrupt Timing As mentioned previously in the buffer mode sec- tions, conflicts between externally reading the buffer RAM and the CS8411 internally writing to it may be averted by using the flag levels to avoid the section currently being addressed by the part. How- ever, if the interrupt line, along with the flags, is utilized, the actual byte that was just updated can be determined. In this way, the entire buffer can be read without concern for internal updates. Figure 15 shows the detailed timing for the interrupt line, flags, and the RAM write line. SCK is 64 times the incoming sample frequency, and is the same SCK output in master mode. The FSYNC shown is valid for all master modes except the I2S compatible mode. The interrupt pulse is shown to be 4 SCK pe- riods wide and goes low 5 SCK periods after the RAM is written. Using the above information, the entire data buffer may be read starting with the next byte to be updated by the internal pointer. ERF Pin Timing ERF signals that an error occurred while receiving the audio sample that is currently being read from the serial port. ERF changes with the active edge of FSYNC and is high during the erroneous sample. ERF is affected by the error conditions reported in SR2: LOCK, CODE, PARITY, and V. Any of these conditions may be masked off using the cor- responding bits in IER2. The ERF pin will go high for each error that occurs. The ERF bit in SR1 is different from the ERF pin in that it only causes an interrupt the first time an error occurs until SR1 is read. More information on the ERF pin and bit is contained at the end of the Status and IEnable Reg- isters section. FSYNC (FLAG0,1) (FLAG2) SCK Left 191 Right 191 Left 0 INT IWRITE INT FSF1,0 MSTR SCED = 1 = 1 = 1 0 Figure 15. RAM/Buffer - Write and Interrupt Timing |
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