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CS8412 Datasheet(PDF) 26 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 26 Page - Cirrus Logic |
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26 / 38 page  CS8411 CS8412 26 DS61F1 C, U, VERF, ERF, and CBL Serial Outputs The C and U bits and CBL are output one SCK pe- riod prior to the active edge of FSYNC in all serial port formats except 2, 3 and 9 (I2S modes). The ac- tive edge of FSYNC may be used to latch C, U, and CBL externally. In formats 2, 3 and 9, the C and U bits and CBL are updated with the active edge of FSYNC. The validity + error flag (VERF) and the error flag (ERF) are always updated at the active edge of FSYNC. This timing is illustrated in Figure 19. The C output contains the channel status bits with CBL rising indicating the start of a new channel status block. CBL is high for the first four bytes of channel status (32 frames or 64 samples) and low for the last 20 bytes of channel status (160 frames or 320 samples). The U output contains the User Channel data. The Vbit is OR’ed with the ERF flag and output on the VERF pin. This indicates that the audio sample may be in error and can be used by in- terpolation filters to interpolate through the error. ERF being high indicates a serious error occurred on the transmission line. There are three errors that cause ERF to go high: a parity error or biphase coding violation during that sample, or an out of lock PLL receiver. Timing for the above pins is il- lustrated in Figure 19. Multifunction Pins There are seven multifunction pins which contain either error and received frequency information, or channel status information, selectable by SEL. No. FSYNC (out) SDATA (out) 13* FSYNC (out) SCK (out) SDATA (out) 12* MSB VU C P LSB AUX MSB VU C P LSB AUX Left Right Left Right MSB VU C P LSB AUX MSB VU C P LSB AUX SCK (out) * Error flags are not accurate in these modes. Figure 18. Special Audio Port Formats 12 and 13 CBL SDATA FSYNC Left 0 Left 1 Right 0 Left 0 Left 32 Right 191 Right 31 Right 191 Ca-Ce C0, ERF, VERF C, U Figure 19. CBL Timing |
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