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CS8412 Datasheet(PDF) 16 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 16 Page - Cirrus Logic |
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16 / 38 page  CS8411 CS8412 16 DS61F1 status byte 15, location 17H is written. If the corre- sponding interrupt enable bit in IER1 is set, a tran- sition of FLAG1 will generate a pulse on the interrupt pin. Figure 12 illustrates the memory write sequence for buffer mode 0 along with flag timing. The arrows on the flag timing indicate when an interrupt will occur if the appropriate in- terrupt enable bit is set. FLAG0 can cause an inter- rupt on either edge, which is only shown in the expanded portion of the figure for clarity. Buffer Mode 1 In buffer mode 1, eight bytes are allocated for chan- nel status data and sixteen bytes for auxiliary data as shown in Figure 5. The user data buffer is the same for all modes. The channel status buffer, loca- tions 08H to 0FH, is divided into two sections. The first four locations always contain the first four bytes of channel status, identical to mode 0, and are written once per channel status block. The second four locations, addresses 0CH to 0FH, provide a cyclic buffer for the last 20 bytes of channel status data. The channel status buffer is divided in this fashion because the first four bytes are the most im- Flag 0 Flag 1 Mode 0 Flag 1 Modes 1 & 2 Flag 2 B 0 A 0 B 1 A 1 B 2 A 2 B 7 A 7 Aux Data 03 4 7 LSB 8 Audio Data Preamble 28 29 30 31 VU CP MSB 27 (384 Audio Samples) 23 012 3 4567 8 9 101112 13 14 15 16 17 18 19 20 21 22 23 01 Channel Status Byte (Expanded) (Expanded) bit Frame Sub-frame Block Validity User Data Channel Status Data Parity Bit Figure 11. CS8411 Status Register Flag Timing |
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Similar Description - CS8412 |
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