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CS8412 Datasheet(PDF) 24 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 24 Page - Cirrus Logic |
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24 / 38 page  CS8411 CS8412 24 DS61F1 wherein the first word past the format number (Out-In) indicates whether FSYNC and SCK are outputs from the CS8412 or are inputs. The next word (L/R-WSYNC) indicates whether FSYNC in- dicates the particular channel or just delineates each word. If an error occurs (ERF = 1) while using one of these formats, the previous valid audio data for that channel will be output. As long as ERF is high, that same data word will be output. If the CS8412 is not locked, it will output all zeroes. In some modes FSYNC and SCK are outputs and in others they are inputs. In Table 3, LSBJ is short for LSB justified where the LSB is justified to the end of the audio frame and the MSB varies with word length. As outputs the CS8412 generates 32 SCK periods per audio sample (64 per stereo sample) and, as inputs, 32 SCK periods must be provided per audio sample. When FSYNC and SCK are in- puts, one stereo sample is double buffered. For those modes which output 24 bits of audio data, the auxiliary bits will be included. If the auxiliary bits are not used for audio data, they must be masked off. Table 3. Normal Audio Port Modes (M3=0) Special Modes (M3 = 1) When M3 is high, the special audio modes de- scribed in Table 4 are selected via M2, M1, and M0. In formats 8, 9, and 10, SCK, FSYNC, and SDATA are the same as in formats 0, 1, and 2 re- spectively; however, the recovered data is output as is even if ERF is high, indicating an error. (In modes 0-2 the previous valid sample is output.) Similarly, when out of lock, the CS8412 will still output all the recovered data, which should be ze- ros if there is no input to the RXP, RXN pins. For- mat 11 is similar to format 0 except that SCK is an input and FSYNC is an output. In this mode FSYNC and SDATA are synchronized to the in- coming SCK, and the number of SCK periods be- tween FSYNC edges will vary since SCK is not synchronous to received data stream. This mode may be useful when writing data to storage. Table 4. Special Audio Port Modes (M3=1) Format 12 is similar to format 7 except that SDA- TA is the entire data word received from the trans- mission line including the C, U, V, and P bits, with zeros in place of the preamble. In format 13 SDA- TA contains the entire biphase encoded data from the transmission line including the preamble, and SCK is twice the normal frequency. The normal two frame delay of data from input to output is re- duced to only a few bit periods in formats 12 and 13. However, the C, U, V bits and error codes fol- low their normal pathways and therefore follow the output data by nearly two frames. Figure 18 illus- trates formats 12 and 13. Format 14 is reserved and not presently used, and format 15 causes the CS8412 to go into a reset state. While in reset all outputs will be inactive except MCK. The CS8412 comes out of reset at the first block boundary after leaving the reset state. It is recommended to reset the CS8412 after power-up and any time the user performs a system-wide reset. A suggested reset circuit is shown in Appendix B. M2 M1 M0 Format 0 0 0 0 - Out, L/R, 16-24 Bits 0 0 1 1 - In, L/R, 16-24 Bits 01 0 2 - Out, L/R, I2S Compatible 01 1 3 - In, L/R, I2S Compatible 1 0 0 4 - Out, WSYNC, 16-24 Bits 1 0 1 5 - Out, L/R, 16 Bits LSBJ 1 1 0 6 - Out, L/R, 18 Bits LSBJ 1 1 1 7 - Out, L/R, MSB Last M2 M1 M0 Format 0 0 0 8 - Format 0 - No repeat on error 0 0 1 9 - Format 1 - No repeat on error 0 1 0 10 - Format 2 - No repeat on error 0 1 1 11 - Format 0 - Async. SCK input 1 0 0 12 - Received NRZ Data 1 0 1 13 - Received Bi-phase Data 1 1 0 14 - Reserved 1 1 1 15 - CS8412 Reset |
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Similar Description - CS8412 |
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