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CS8412 Datasheet(PDF) 20 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 20 Page - Cirrus Logic |
20 / 38 page CS8411 CS8412 20 DS61F1 PIN DESCRIPTIONS: CS8411 Power Supply Connections VD+ - Positive Digital Power, PIN 7. Positive supply for the digital section. Nominally +5 volts. VA+ - Positive Analog Power, PIN 22. Positive supply for the analog section. Nominally +5 volts. This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock. DGND - Digital Ground, PIN 8. Ground for the digital section. DGND should be connected to same ground as AGND. AGND - Analog Ground, PIN 21. Ground for the analog section. AGND should be connected to same ground as DGND. Audio Output Interface SCK - Serial Clock, PIN 12. Serial clock for SDATA pin which can be configured (via control register 2) as an input or output, and can sample data on the rising or falling edge. As an input, SCK must contain 32 clocks for every audio sample in all normal audio serial port formats. 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 DATA BUS BIT 1 DATA BUS BIT 0 SERIAL OUTPUT DATA ERROR FLAG CHIP SELECT READ/WRITE SELECT ANALOG POWER ANALOG GROUND DGND VD+ D7 D6 D5 D4 D3 D2 9 10 11 12 17 18 19 20 FILTER MASTER CLOCK ADDRESS BUS BIT 0 ADDRESS BUS BIT 1 SCK FSYNC RXN RXP 13 14 15 16 ADDRESS BUS BIT 2 ADDRESS BUS BIT 3 INT A4/FCK D1 D0 SDATA ERF CS RD/WR VA+ AGND FILT MCK A0 A1 A2 A3 DIGITAL GROUND DIGITAL POWER DATA BUS BIT 7 DATA BUS BIT 6 DATA BUS BIT 5 DATA BUS BIT 4 DATA BUS BIT 3 DATA BUS BIT 2 SERIAL DATA CLOCK FRAME SYNC RECEIVE NEGATIVE RECEIVE POSITIVE INTERRUPT ADD BUS BIT 4 / FCLOCK CS8411 |
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