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CS8412 Datasheet(PDF) 9 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 9 Page - Cirrus Logic |
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9 / 38 page  CS8411 CS8412 DS61F1 9 status registers are visible and all interrupts are dis- abled. The IER/SR bit must be set to make the IEn- able registers visible. Status register 1 (SR1), shown in Figure 6, reports all the conditions that can generate a low pulse, four SCLK cycles wide, on the interrupt pin (INT). The three least significant bits, FLAG2-FLAG0, are used to monitor the ram buffer. These bits con- tinually change and indicate the position of the buffer pointer which points to the buffer memory location currently being written. Each flag has a corresponding interrupt enable bit in IEnable regis- ter 1 which, when set, allows a transition on the flag to generate a pulse on the interrupt pin. FLAG0 and FLAG1 cause interrupts on both edges whereas FLAG2 causes an interrupt on the rising edge only. Further information, including timing, on the flags can be found in the Buffer Memory section. The next five bits; ERF, SLIP, CCHG, CRCE/CRC1, and CSDIF/CRC2, are latches which are set when their corresponding conditions occur, and are reset when SR1 is read. Interrupt pulses are generated the first time that condition oc- curs. If the status register is not read, further in- stances of that same condition will not generate another interrupt. ERF is the error flag bit and is set when the ERF pin goes high. It is an OR’ing of the errors listed in status register 2, bits 0 through 4, AND’ed with their associated interrupt enable bits in IEnable register 2. A4/ 13 VA+ FILT AGND MCK 19 21 22 20 9 10 SDATA 23 24 FCK A0- A3 D0- D7 48 11 SCK FSYNC 12 26 CS RD/WR 4 X 8 25 ERF 14 INT Buffer Memory 28 X 8 Control Registers 2 X 8 De-Multiplexor Audio Serial Port C.S. user aux crc check no lock Bi-phase parity validity crc slipped RXP RXN 7 8 VD+ DGND Clock & Data Recovery Bi-phase Decoder Frequency Comparator IEnable & Status Figure 4. CS8411 Block Diagram |
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