6

LTC1662

OUTPUT SOURCE/SINK CURRENT (mA)

1662 G16

3.0

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

CODE = 1023

CODE = 0

TIME (0.5ms/DIV)

1662 G17

5

4

3

2

1

0

0

10% TO 90% STEP

CAPACITANCE (F)

100p 1000p 0.01

µ 0.1µ

1

µ

10

µ

100

µ

1662 G18

180

160

140

120

100

80

60

40

20

0

TYPICAL PERFOR A CE CHARACTERISTICS

Max/Min Output Voltage vs Source/

Large-Signal Step Response

Output Minimum Series

Resistance vs Load Capacitance

CS/LD (Pin 1): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on SDI

into the register. When CS/LD is pulled high, SCK is

disabled and the operation(s) specified in the Control

code, A3-A0, is (are) performed. CMOS and TTL compat-

ible.

SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL

compatible.

SDI (Pin 3): Serial Interface Data Input. Input word data on

the SDI pin is shifted into the 16-bit register on the rising

edge of SCK. CMOS and TTL compatible.

REF (Pin 4): Reference Voltage Input. 0V

The output range is

0

1023

1024

≤≤









VV

V

OUTA

OUTB

REF

,

GND (Pin 7): System Ground.

PI FU CTIO S

Gain Error (GE): The deviation from the slope of the ideal

DAC transfer function, expressed in LSBs at full scale.

Integral Nonlinearity (INL): The deviation from a straight

line passing through the endpoints of the DAC transfer

curve (Endpoint INL). Because the output cannot go below

zero, the linearity is measured between full scale and the

lowest code which guarantees the output will be greater

than zero. The INL error at a given input code is calculated

as follows:

Differential Nonlinearity (DNL): The difference between

the measured change and the ideal 1LSB change for any

two adjacent codes. The DNL error between any two codes

is calculated as follows:

DNL = (

where

two adjacent codes.

Full-Scale Error (FSE): The deviation of the actual full-

scale voltage from ideal. FSE includes the effects of offset

and gain errors (see Figure 2).

DEFI ITIO S