7

LTC1662

TI I G DIAGRA

SDI

CS/LD

SCK

A3

A2

1662 TD

A1

X1

X0

DEFI ITIO S

SDI

SCK

CS/LD

A3

A2

INPUT CODE

DON’T CARE

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X1

X0

1662 F01

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

(SCK ENABLED)

(INSTRUCTION

EXECUTED)

CONTROL CODE

Figure 1. Register Loading Sequence

the given input code.

Least Significant Bit (LSB): The ideal voltage difference

between two successive codes.

Resolution (n): Defines the number of DAC output states

imply linearity.

output when the DAC is loaded with all zeros. A single

supply DAC can have a true negative offset, but the output

cannot go below zero (see Figure 2).

For this reason, single supply DAC offset is measured at

the lowest code that guarantees the output will be greater

than zero.

OPERATIO