| Electronic Components Datasheet Search |
|
R8C/20 Datasheet(PDF) 256 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R8C/20 Datasheet(HTML) 256 Page - Renesas Technology Corp |
|
256 / 501 page ![]() R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 240 of 458 REJ09B0250-0200 Figure 14.100 Registers TRDMR and TRDFCR in PWM3 Mode Timer RD Mode Register Symbol Address After Reset TRDMR 0138h 00001110b Bit Symbol Bit Name Function RW b3 b2 BFD0 b1 b0 SYNC b7 b6 b5 b4 RW — (b3 - b1) — Timer RD synchronous bit This bit is disabled in PWM3 mode. Nothing is assigned. If necessary, set to 0. When read, the content is 1. RW TRDGRD0 register function selection bit 0 : General register 1 : Buffer register of TRDGRB0 register TRDGRC1 register function selection bit 0 : General register 1 : Buffer register of TRDGRA1 register RW TRDGRC0 register function selection bit 0 : General register 1 : Buffer register of TRDGRA0 register BFC0 RW RW BFC1 BFD1 TRDGRD1 register function selection bit 0 : General register 1 : Buffer register of TRDGRB1 register Timer RD Function Control Register Symbol Address After Reset TRDFCR 013Ah 10000000b Bit Symbol Bit Name Function RW NOTES: 1. 2. STCLK External clock input selection bit Set this bit to 0 (external clock input disabled) in PWM3 mode. RW RW PWM3 RW ADTRG ADEG A/D trigger edge selection bit (enabled in complementary PWM mode) This bit is disabled in PWM3 mode. RW PWM3 mode selection bit(2) Set this bit to 0 (PWM3 mode) in PWM3 mode. Normal-phase output level selection bit (enabled in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in PWM3 mode. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). OLS0 RW RW Counter-phase output level selection bit (enabled in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in PWM3 mode. A/D trigger enable bit (enabled in complementary PWM mode) This bit is disabled in PWM3 mode. RW CMD1 RW Combination mode selection bit(1) Set to 00b (timer mode, PWM mode, or PWM3 mode) in PWM3 mode. CMD0 b7 b6 b5 b4 00 When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. b3 b2 OLS1 b1 b0 00 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |