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BS640HD9V Datasheet(PDF) 59 Page - Advanced Micro Devices

Part # BS640HD9V
Description  128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
PDF  89 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

BS640HD9V Datasheet(HTML) 59 Page - Advanced Micro Devices

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May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
57
D A TA
SH EE T
AC CHARACTERISTICS
Synchronous/Burst Read
Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
Parameter
Description
66 MHz
54 MHz
Unit
JEDEC
Standard
tIACC
Latency (Even address in Reduced wait-state
Handshaking mode)
Max
56
69
ns
tIACC
Latency (Standard Handshaking or Odd
address in Reduced wait-state Handshaking
mode
Max
71
87.5
ns
tBACC
Burst Access Time Valid Clock to Output
Delay
Max
11
13.5
ns
tACS
Address Setup Time to CLK (Note )
Min
4
5
ns
tACH
Address Hold Time from CLK (Note )
Min
6
7
ns
tBDH
Data Hold Time from Next Clock Cycle
Min
3
4
ns
tCR
Chip Enable to RDY Valid
Max
11
13.5
ns
tOE
Output Enable to Output Valid
Max
11
13.5
ns
tCEZ
Chip Enable to High Z
Max
8
10
ns
tOEZ
Output Enable to High Z
Max
8
10
ns
tCES
CE# Setup Time to CLK
Min
4
5
ns
tRDYS
RDY Setup Time to CLK
Min
4
5
ns
tRACC
Ready Access Time from CLK
Max
11
13.5
ns
tAAS
Address Setup Time to AVD# (Note )
Min
4
5
ns
tAAH
Address Hold Time to AVD# (Note )
Min
6
7
ns
tCAS
CE# Setup Time to AVD#
Min
0
ns
tAVC
AVD# Low to CLK
Min
4
5
ns
tAVD
AVD# Pulse
Min
10
12
ns
tACC
Access Time
Max
50
55
ns
tCKA
CLK to access resume
Max
11
13.5
ns
tCKZ
CLK to High Z
Max
8
10
ns
tOES
Output Enable Setup Time
Min
4
5
ns
tRCC
Read cycle for continuous suspend
Max
1
ms



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