BS640HD9V datasheet(37/89 Pages) AMD

37 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

Standard Handshaking Option

For optimal burst mode performance on devices with

the standard handshaking option, the host system

must set the appropriate number of wait states in the

flash device depending on the clock frequency.

Table 16 describes the typical number of clock cycles

(wait states) for various conditions with A14-A12 set to

101.

Table 16.

Wait States for Standard Handshaking

* In the 8-, 16- and 32-word burst read modes, the address

pointer does not cross 64-word boundaries (addresses

which are multiples of 3Fh).

The autoselect function allows the host system to

determine whether the flash device is enabled for

ha ndsha king. See t he “Auto s elect Co mmand

Sequence” section on page 36 for more information.

Read Mode Configuration

The device supports four different read modes: contin-

uous mode, and 8, 16, and 32 word linear wrap around

modes. A continuous sequence begins at the starting

address and advances the address pointer until the

burst operation is complete. If the highest address in

the device is reached during the continuous burst read

mode, the address pointer wraps around to the lowest

address.

For example, an eight-word linear read with wrap

around begins on the starting address written to the

device and then advances to the next 8 word boundary.

The address pointer then returns to the 1st word after

the previous eight word boundary, wrapping through

the starting location. The sixteen- and thirty-two linear

wrap around modes operate in a fashion similar to the

eight-word mode.

Table 17 shows the address bits and settings for the

four read modes.

Table 17.

Read Mode Settings

Note: Upon power-up or hardware reset the default setting is

continuous.

Burst Active Clock Edge Configuration

By default, the device will deliver data on the rising

edge of the clock after the initial synchronous access

time. Subsequent outputs will also be on the following

rising edges, barring any delays. The device can be set

so that the falling clock edge is active for all synchro-

nous accesses. Address bit A17 determines this set-

ting; “1” for rising active, “0” for falling active.

RDY Configuration

By default, the device is set so that the RDY pin will

output VOH whenever there is valid data on the outputs.

The device can be set so that RDY goes active one

data cycle before active data. Address bit A18 deter-

mines this setting; “1” for RDY active with data, “0” for

RDY active one clock cycle before valid data. In asyn-

chronous mode, RDY is an open-drain output.

Configuration Register

Table 18 shows the address bits that determine the

configuration register settings for various device func-

tions.

Conditions at Address

Typical No. of Clock

Cycles after AVD# Low

Initial address

Initial address is 3E or 3Fh (or

offset from these addresses by

a multiple of 64) and is at

boundary crossing*

Burst Modes

Address Bits

A16

A15

Continuous

8-word linear wrap around

16-word linear wrap around

32-word linear wrap around

BS640HD9V Datasheet(PDF) 37 Page - Advanced Micro Devices

BS640HD9V Datasheet(HTML) 37 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Datasheet Download

Link URL