BS640HD9V datasheet(54/89 Pages) AMD

54 / 89 page

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A TA

SH EE T

device will accept additional sector erase commands.

To ensure the command has been accepted, the

system software should check the status of DQ3 prior

to and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

Table 23 shows the status of DQ3 relative to the other

status bits.

Table 23.

Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

4. The system may read either asynchronously or synchronously (burst) while in erase suspend.

5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This

is available in the Asynchronous mode only.

Status

DQ7

(Note 2)

DQ6

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

RDY (Note

Standard

Mode

Embedded Program Algorithm

DQ7#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

Erase

Suspend

Mode

Erase-Suspend-

Read (Note 4)

Erase

Suspended Sector

No toggle

N/A

Toggle

High

Impedance

Non-Erase

Suspended Sector

Data

High

Impedance

Erase-Suspend-Program

DQ7#

Toggle

N/A

BS640HD9V Datasheet(PDF) 54 Page - Advanced Micro Devices

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