BS640HD9V datasheet(52/89 Pages) AMD

52 / 89 page

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A TA

SH EE T

Figure 9.

Toggle Bit Algorithm

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. But DQ2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ6, by com-

parison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both

status bits are required for sector and mode informa-

tion. Refer to Table 22, “DQ6 and DQ2 Indications,” on

page 51 to compare outputs for DQ2 and DQ6.

See the following for additional information: Figure 9,

“Toggle Bit Algorithm,” on page 50, “DQ6: Toggle Bit I”

on p a g e 49 , F i gu re 41, “ To ggle Bit Tim i n g s

(During Embedded Algorithm),” on page 76, and

Table 22, “DQ6 and DQ2 Indications,” on page 51.

START

Yes

DQ5 = 1?

Yes

DQ6 = Toggle?

Read Byte

(DQ7-DQ0)

Address = VA

DQ6 = Toggle?

Read Byte Twice

(DQ7-DQ0)

Adrdess = VA

Read Byte

(DQ7-DQ0)

Address = VA

FAIL

PASS

Note:The system should recheck the toggle bit even if DQ5 =

“1” because the toggle bit may stop toggling as DQ5 changes

to “1.” See the subsections on DQ6 and DQ2 for more

information.

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