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BS640HD9V Datasheet(PDF) 26 Page - Advanced Micro Devices |
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BS640HD9V Datasheet(HTML) 26 Page - Advanced Micro Devices |
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26 / 89 page ![]() 24 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A TA SH EE T Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previ- ously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the eight “out- ermost” 4 Kword boot sectors. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in “PPB Program Command” sec- tion on page 43. Note that the WP# pin must not be left floating or un- connected; inconsistent behavior of the device may re- sult. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-indepen- dent, JEDEC ID-independent, and forward- and back- ward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Quer y command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 8-11. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8-11. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the AMD site at the following URL: http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies Table 8. CFI Query Identification String Addresses Data Description 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) |
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