R8CSLASH20 datasheet(261/501 Pages) RENESAS

261 / 501 page

R8C/20 Group, R8C/21 Group

14. Timers

Rev.2.00 Aug 27, 2008

Page 245 of 458

REJ09B0250-0200

Figure 14.105 Registers TRDIER0 and TRDIER1 in PWM3 Mode

Figure 14.106 TRD0 Register in PWM3 Mode

Timer RD Interrupt Enable Register i (i = 0 or 1)

Symbol

Address

After Reset

TRDIER0

0144h

11100000b

TRDIER1

0154h

11100000b

Bit Symbol

Bit Name

Function

b3 b2

IMIED

b1 b0

b7 b6 b5 b4

IMIEB

Input capture/compare match

interrupt enable bit A

0 : Disable an interrupt (IMIA) by the

IMFA bit

1 : Enable an interrupt (IMIA) by the

IMFA bit

Input capture/compare match

interrupt enable bit B

0 : Disable an interrupt (IMIB) by the

IMFB bit

1 : Enable an interrupt (IMIB) by the

IMFB bit

IMIEA

Input capture/compare match

interrupt enable bit C

0 : Disable an interrupt (IMIC) by the

IMFC bit

1 : Enable an interrupt (IMIC) by the

IMFC bit

IMIEC

Input capture/compare match

interrupt enable bit D

0 : Disable an interrupt (IMID) by the

IMFD bit

1 : Enable an interrupt (IMID) by the

IMFD bit

Overflow /underflow interrupt enable

bit

0 : Disable an interrupt (OVI) by the

OVF bit

1 : Enable an interrupt (OVI) by the

OVF bit

OVIE

—

(b7 - b5)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 1.

Timer RD Counter 0

(1,2)

Symbol

Address

After Reset

TRD0

0147h-0146h

0000h

Setting Range

NOTES:

Function

Count a count source. Count operation is incremented.

When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.

0000h to FFFFh

The TRD1 register is not used in PWM3 mode.

(b8)

(b15)

Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.

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