R8CSLASH20 datasheet(243/501 Pages) RENESAS

243 / 501 page

R8C/20 Group, R8C/21 Group

14. Timers

Rev.2.00 Aug 27, 2008

Page 227 of 458

REJ09B0250-0200

Figure 14.89

TRDFCR Register in Complementary PWM Mode

Timer RD Function Control Register

Symbol

Address

After Reset

TRDFCR

013Ah

10000000b

Bit Symbol

Bit Name

Function

NOTES:

4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is

enabled.

b3 b2

OLS1

b1 b0

b7 b6 b5 b4

CMD1

Combination mode selection bit(1,2)

b1 b0

1 0 : Complementary PWM mode

(transfer from the

buffer register to the general

the TRD1 register.)

1 1 : Complementary PWM mode

(transfer from the

buffer register to the general

the TRD0 and TRDGRA0 registers.)

Other than above : Do not set

CMD0

Normal-phase output level selection

bit (in reset synchronous PWM mode

or complementary PWM mode)

0 : Initial output “H”

Active level “L”

1 : Initial output “L”

Active level “H”

Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops).

OLS0

Counter-phase output level selection

bit (in reset synchronous PWM mode

or complementary PWM mode)

0 : Initial output “H”

Active level “L”

1 : Initial output “L”

Active level “H”

A/D trigger enable bit

(in complementary PWM mode)

0 : Disable A/D trigger

1 : Enable A/D trigger(3)

PWM3

ADTRG

ADEG

A/D trigger edge selection bit

(in complementary PWM mode)

0 : A/D trigger is generated at the

compare match in the TRD0 and

TRDGRA0 register

1 : A/D trigger is generated at the

underflow in the TRD1

PWM3 mode selection bit(4)

This bit is disabled in complementary PWM

mode.

Set the ADCAP bit in the ADC0N0 register to 1 (starts by timer RD).

When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of

the TRDPMR register.

STCLK

External clock input selection bit

0 : External clock input disabled

1 : External clock input enabled

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