R8CSLASH20 datasheet(105/501 Pages) RENESAS

105 / 501 page

R8C/20 Group, R8C/21 Group

12. Interrupts

Rev.2.00 Aug 27, 2008

Page 89 of 458

REJ09B0250-0200

12.1.3

Special Interrupts

Special interrupts are non-maskable interrupts.

12.1.3.1

Watchdog Timer Interrupt

The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer.

12.1.3.2

Oscillation Stop Detection Interrupt

Oscillation Stop Detection Interrupt is generated by the oscillation stop detection function. For details of the

oscillation stop detection function, refer to 10. Clock Generation Circuit.

12.1.3.3

Voltage Monitor 2 Interrupt

The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage

detection circuit, refer to 6. Voltage Detection Circuit.

12.1.3.4

Single-Step Interrupt, and Address Break Interrupt

Do not use the single-step interrupt. For development tools only.

12.1.3.5

Address Match Interrupt

The address match interrupt is generated immediately before executing an instruction that is stored into an

address indicated by the RMAD0 to RMAD1 registers when the AIER0 or AIER1 bit in the AIER register

which is set to 1 (address match interrupt enable).

For details of the address match interrupt, refer to 12.4 Address Match Interrupt.

12.1.4

Peripheral Function Interrupt

The peripheral function interrupt is generated by the internal peripheral function of the MCU and a maskable

interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For

details of the peripheral function, refer to the description of each peripheral function.

R8C/20 Datasheet(PDF) 105 Page - Renesas Technology Corp