R8CSLASH20 datasheet(109/501 Pages) RENESAS

109 / 501 page

R8C/20 Group, R8C/21 Group

12. Interrupts

Rev.2.00 Aug 27, 2008

Page 93 of 458

REJ09B0250-0200

Figure 12.4

Registers TRD0IC, TRD1IC, SSUIC, and IICIC

Interrupt Control Register

(1)

Symbol

Address

After Reset

TRD0IC

0048h

XXXXX000b

TRD1IC

0049h

XXXXX000b

SSUIC/IICIC(2)

004Fh

XXXXX000b

Bit Symbol

Bit Name

Function

NOTES:

—

(b7-b4)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Interrupt request bit

0 : Requests no interrupt

1 : Requests interrupt

ILVL0

Interrupt priority level select bits b2 b1 b0

0 0 0 : Level 0 (interrupt disable)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

ILVL1

ILVL2

The IICSEL bit in the PMR register sw itches functions.

To rew rite the interrupt control register, rew rite it w hen the interrupt request w hich is applicable for its register is not

generated. Refer to 12.6.5 Changing Interrupt Control Register Contents.

b7 b6 b5 b4 b3 b2 b1 b0

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