R8CSLASH20 datasheet(101/501 Pages) RENESAS

101 / 501 page

R8C/20 Group, R8C/21 Group

10. Clock Generation Circuit

Rev.2.00 Aug 27, 2008

Page 85 of 458

REJ09B0250-0200

10.6

Notes on Clock Generation Circuit

10.6.1

Stop Mode

When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and the CM10 bit to “1” (stop

mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register

to “1” (stop mode) and the program stops. Insert at least 4 NOP instructions following the JMP.B instruction

immediately after the instruction which sets the CM10 bit to “1”.

• Example to enter stop mode

BCLR

1,FMR0

; CPU rewrite mode disabled

BSET

0,PRCR

; Protect disabled

FSET

; Enable interrupt

BSET

0,CM1

; Stop mode

JMP.B

LABEL_001

LABEL_001:

NOP

10.6.2

Wait Mode

When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and execute the WAIT

instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at

least 4 NOP instructions after the WAIT instruction.

• Example to execute the WAIT instruction

BCLR

1,FMR0

; CPU rewrite mode disabled

FSET

; Enable interrupt

WAIT

; Wait mode

NOP

10.6.3

Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be used if the XIN clock frequency is less than 2 MHz, set

the OCD1 to OCD0 bits to 00b.

10.6.4

Oscillation Circuit Constants

Ask the maker of the oscillator to specify the beat oscillation circuit constants on your system.

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