Data Sheet

ADSP1802

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. D | 21 of 34

Figure 30. Pin Configuration

Table 36. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1, 7

CLK_CFG1, CLK_CFG0 I

Core to CLKIN Ratio Control. These pins set the startup clock frequency. Note that the operating

frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any

time after the core comes out of reset. The allowed values are: 00 = 8:1, 01 = 32:1, 10 = 16:1, 11 =

reserved.

2, 5

BOOT_CFG0,

BOOT_CFG1

I

Boot Configuration Select. These pins select the boot mode for the processor. The BOOT_CFG pins

must be valid before RESET (hardware and software) is asserted.

3, 11, 23, 40, 47, 75,

81

VDD_EXT

P

I/O Power Supply.

4, 8, 12, 13, 15, 19,

33, 39, 41, 46, 49,

59, 64 to 67, 69, 77,

82, 85, 88

VDD_INT

P

Internal Power Supply.

6, 60, 73, 74, 76

GND

G

Ground.

9

CLKIN

I

Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures the processor

to use either its internal clock generator or an external clock source. Connecting the necessary

components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock

to CLKIN while leaving XTAL unconnected configures the processor to use the external clock source

such as an external clock oscillator. CLKIN must not be halted, changed, or operated below specified

frequency.

10

XTAL

O

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.

14

RESETOUT/RUNRSTIN I (IPU)

Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also has a second

function as RUNRSTIN, which is enabled by setting bit 0 of the RUNRSTCTL register.

16 to 182, 20 to 222,

24 to 302, 322

DPI_P01 to DPI_P14

I/O/T (IPU)

DPI. These pins provide the physical interface to the DPI SRU. The DPI SRU configuration registers

define the combination of on-chip peripheral inputs or outputs connected to the pin and to the output

enable of the pin. The configuration registers of these peripherals then determine the exact behavior of

the pin. Any input or output signal present in the DPI SRU can be routed to any of these pins.

312, 34 to 382, 42 to

452, 48, 50 to 582

DAI_P01 to DAI_P20

I/O/T (IPU)

DAI. These pins provide the physical interface to the DAI SRU. The DAI SRU configuration registers

define the combination of on-chip audio centric peripheral inputs or outputs connected to the pin and to

the output enable of the pin. The configuration registers of these peripherals then determine the exact

behavior of the pin. Any signal present in the DAI SRU can be routed to any of these pins.

61

THD_M

O

Thermal Diode Cathode. When not used, this pin can be left floating.

62

THD_P

I

Thermal Diode Anode. When not used, this pin can be left floating.

63

VDD_THD

P

Thermal Diode Power Supply. When not used, this pin can be left floating.