Data Sheet

ADSP1802

SPECIFICATIONS

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Rev. D | 12 of 34

Table 19. Serial Ports—Input Data Port (IDP) (Continued)

Parameter

Description

Min

Max

Unit

tSIHFS1

Frame Sync Hold After Serial Clock Rising Edge

2.5

ns

tSISD1

Data Setup Before Serial Clock Rising Edge

2.5

ns

tSIHD1

Data Hold After Serial Clock Rising Edge

2.5

ns

t IDPCLKW

Clock Width

(tPCLK × 4) ÷ 2 – 1

ns

t IDPCLK

Clock Period

tPCLK × 4

ns

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG input

can be either the CLKIN pin or any of the DAI pins.

Figure 17. IDP Main Timing

Parallel Data Acquisition Port (PDAP)

PDAP is the parallel mode operation of Channel 0 of the IDP.

Table 20. PDAP

Parameter

Description

Min

Max

Unit

TIMING REQUIREMENTS

tSPHOLD1

PDAP_HOLD Setup Before PDAP_CLK Sample Edge

2.5

ns

tHPHOLD1

PDAP_HOLD Hold After PDAP_CLK Sample Edge

2.5

ns

tPDSD1

PDAP_DAT Setup Before PDAP_CLK Sample Edge

3.85

ns

tPDHD1

PDAP_DAT Hold After PDAP_CLK Sample Edge

2.5

ns

tPDCLKW

Clock Width

(tPCLK × 4) ÷ 2 − 3

ns

t PDCLK

Clock Period

tPCLK × 4

ns

SWITCHING CHARACTERISTICS

ns

tPDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

2 × tPCLK + 3

ns

tPDSTRB

PDAP Strobe Pulse Width

2 × tPCLK − 1.5

ns

1 Source pins of PDAP_DATA are DAI pins. Source pins for PDAP_CLK and PDAP_HOLD are DAI pins, CLKIN through PCG, and DAI pins through PCG.

Figure 18. PDAP Timing