Data Sheet

ADSP1802

SPECIFICATIONS

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Rev. D | 7 of 34

Timer WDTH_CAP Timing

The following timing specification applies to Timer0 and Timer1, and in WDTH_CAP (pulse width count and capture) mode. Timer signals are

routed to the DPI_P1 to DPI_P14 pins through the SRU. Therefore, the timing specification provided in Table 10 is valid at the DPI_P1 to

DPI_P14 pins.

Table 10. Timer Width Capture Timing

Parameter

Description

Min

Max

Unit

TIMING REQUIREMENT

tPWI

Timer Pulse Width

2 × tPCLK

2 × (231 − 1) × tPCLK

ns

Figure 9. Timer Width Capture Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O).

Table 11. DAI/DPI Pin to Pin Routing

Parameter

Description

Min

Max

Unit

TIMING REQUIREMENT

tDPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid

1.5

12

ns

Figure 10. DAI/DPI Pin to Pin Routing

Precision Clock Generators (PCGs) (Direct Pin Routing)

This timing is only valid when the SRU is configured such that the PCG takes its inputs directly from the DAI pins (via pin buffers) and sends its

outputs directly to the DAI pins. For the other cases, where the PCG inputs and outputs are not directly routed to/from DAI pins (via pin buffers),

there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 to DAI_P20)

Table 12. PCG (Direct Pin Routing)

Parameter

Description

Min

Max

Unit

TIMING REQUIREMENTS

tPCGIW

Input Clock Period

tPCLK × 4

ns

tSTRIG

PCG Trigger Setup Before Falling Edge of PCG Input Clock 4.5

ns

tHTRIG

PCG Trigger Hold After Falling Edge of PCG Input Clock

3

ns

SWITCHING

CHARACTERISTICS

tDPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After

PCG Input Clock

2.5

10

ns

tDTRIGCLK

PCG Output Clock Delay After PCG Trigger

2.5 + (2.5 × tPCGIP)

10 + (2.5 × tPCGIP)

ns

tDTRIGFS

PCG Frame Sync Delay After PCG Trigger

2.5 + ((2.5 + D – PH) ×

tPCGIP)1

10 + ((2.5 + D – PH) × tPCGIP)1 ns

tPCGOW2

Output Clock Period

2 × tPCGIP – 1

ns

1 D = FSxDIV means divisor for frame sync of PCG A, PCG B, PCG C, and PCG D. PH = FSxPHASE means phase for frame sync of PCG A, PCG B, PCG C, and PCG D.