Data Sheet

ADSP1802

SPECIFICATIONS

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Rev. D | 4 of 34

Consequently, it is not meaningful to add parameters to derive longer times. Switching characteristics specify how the processor changes

its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics

describe what the processor does in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device

connected to the processor (such as memory) is satisfied.

Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation.

Timing requirements guarantee that the processor operates correctly with other devices.

Power-Up Sequencing

The timing requirements for processor startup are shown in Table 3. While no specific power-up sequencing is required between VDD_EXT and

VDD_INT, review the following system design considerations:

►

No power supply must be powered up for an extended period of time (>200 ms) before another supply starts to ramp up.

►

If the VDD_INT power supply comes up after the VDD_EXT, any pin, such as RESETOUT and RESET, may actually drive momentarily until the

VDD_INT rail has powered up. Systems sharing these signals on the board must determine if there are any issues that must be addressed

based on this behavior.

Note that during power-up, when the VDD_INT power supply comes up after VDD_EXT, a leakage current of the order of three-state leakage

current pull-up, even if that is an input only (for example the RESET pin) until the VDD_INT rail has powered up.

Table 3. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter

Description

Min

Max

Unit

TIMING REQUIREMENTS

tRSTVDD

RESET Low Before VDD_EXT or VDD_INT On

0

ms

tIVDDEVDD

VDD_INT On Before VDD_EXT

–200

+200

ms

tCLKVDD1

CLKIN Valid After VDD_INT and VDD_EXT Valid

0

200

ms

tCLKRST

CLKIN Valid Before RESET Deasserted

102

μs

tPLLRST

PLL Control Setup Before RESET Deasserted

203

μs

SWITCHING CHARACTERISTICS

tCORERST4,5

Core Reset Deasserted After RESET Deasserted

4096 × tCK + 2 × tCCLK

1 Valid VDD_INT and VDD_EXT assume that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary

from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.

2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

3 Based on CLKIN cycles.

4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

5 The 4096 cycle count depends on tSRST specification in Table 5. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

Figure 2. Power-Up Sequencing