Data Sheet

ADSP1802

SPECIFICATIONS

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Rev. D | 8 of 34

2 Normal mode of operation.

Figure 11. PCG (Direct Pin Routing)

Flags

The timing specifications provided in Table 13 apply to the DPI_P1 to DPI_P14 and FLAG0 to FLAG3 pins when configured as flags.

Table 13. Flags

Parameter

Description

Min

Max

Unit

TIMING REQUIREMENT

tFIPW1

FLAG0 to FLAG3 Input Pulse Width

2 × tPCLK + 3

ns

SWITCHING CHARACTERISTIC

tFOPW1

FLAG0 to FLAG3 Output Pulse Width

2 × tPCLK − 3

ns

1 This is applicable when the flags are connected to DPI_P1 to DPI_P14 and FLAG0 to FLAG3 pins.

Figure 12. Flags

Serial Ports (SPORTs)

In subordinate transmitter mode and main receiver mode, the maximum SPORT frequency is fPCLK/8. In main transmitter mode and subordinate

receiver mode, the maximum SPORT clock frequency is fPCLK/4. To determine whether communication is possible between two devices at clock

speed n, the following specifications must be confirmed:

►

Frame sync delay and frame sync setup and hold

►

Data delay and data setup and hold

►

SCLK width

SPORT signals (SCLK, frame sync, Data Channel A, and Data Channel B) are routed to the DAI_P1 to DAI_P20 pins using the SRU.

Therefore, the timing specifications provided in Table 14, Table 15, Table 16, Table 17, and Table 18 are valid at the DAI_P1 to DAI_P20 pins.

Table 14. SPORTs—External Clock

Parameter

Description

Min

Max

Unit

TIMING REQUIREMENTS

tSFSE1

Frame Sync Setup Before SCLK (Externally Generated Frame Sync in

Either Transmit or Receive Mode)

2.5

ns