ADSP1802 datasheet(32/34 Pages) AD

32 / 34 page

Data Sheet

ADSP1802

THEORY OF OPERATION

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Rev. D | 32 of 34

operations to occur while the core is simultaneously executing its

program instructions. DMA transfers can occur between the internal

memory, SPORTs, SPI ports, IDP, PDAP, or the UART port of the

ADSP1802. The DMA channel summary is shown in Table 44.

Programs can be downloaded to the ADSP1802 using DMA trans-

fers. Other DMA features include interrupt generation upon comple-

tion of DMA transfers and DMA chaining for automatic linked DMA

transfers.

Table 44. DMA Channels

Peripheral

DMA Channels

SPORTs

IDP/PDAP

SPI

UART

External Port

Accelerators

MTM

FFT Accelerator

The FFT accelerator implements a radix two complex/real input,

complex output FFT with no core intervention. The FFT accelerator

runs at the peripheral clock frequency.

FIR Accelerator

The FIR accelerator consists of a 1024 words coefficient memory,

a 1024 words deep delay line for the data, and four MAC units. A

controller manages the accelerator. The FIR accelerator runs at the

peripheral clock frequency.

IIR Accelerator

The IIR accelerator consists of a 1440 words coefficient memory

for storage of biquad coefficients, a data memory for storing the

intermediate data, and one MAC unit. A controller manages the ac-

celerator. The IIR accelerator runs at the peripheral clock frequency.

ADSP1802 Datasheet(PDF) 32 Page - Analog Devices