Data Sheet

ADSP1802

SPECIFICATIONS

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Rev. D | 13 of 34

Sample Rate Converter (SRC)—Serial Input Port

The asynchronous sample rate converter (ASRC) input signals are routed from the DAI_P1 to DAI_P20 pins using the SRU. Therefore, the

timing specifications provided in Table 21 are valid at the DAI_P1 to DAI_P20 pins.

Table 21. ASRC, Serial Input Port

Parameter

Description

Min

Max

Unit

TIMING REQUIREMENTS

tSRCSFS 1

Frame Sync Setup Before Serial Clock Rising Edge

4

ns

tSRCHFS1

Frame Sync Hold After Serial Clock Rising Edge

5.5

ns

tSRCSD1

Data Setup Before Serial Clock Rising Edge

4

ns

tSRCHD1

Data Hold After Serial Clock Rising Edge

5.5

ns

tSRCCLKW

Clock Width

(tPCLK × 4) ÷ 2 − 1

ns

tSRCCLK

Clock Period

tPCLK × 4

ns

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG input

can be either CLKIN or any of the DAI pins.

Figure 19. ASRC Serial Input Port Timing

SRC—Serial Output Port

For the serial output port, the frame sync is an input, and it must meet setup and hold times about SCLK on the output port. The serial data

output has a hold time and delay specification about serial clock. Note that serial clock rising edge is the sampling edge, and the falling edge is

the drive edge.

Table 22. ASRC, Serial Output Port

Parameter

Description

Min

Max

Unit

TIMING REQUIREMENTS

tSRCSFS1

Frame Sync Setup Before Serial Clock Rising Edge

4

ns

tSRCHFS1

Frame Sync Hold After Serial Clock Rising Edge

5.5

ns

tSRCCLKW

Clock Width

(tPCLK × 4) ÷ 2 − 1

ns

tSRCCLK

Clock Period

tPCLK × 4

ns

SWITCHING CHARACTERISTICS

tSRCTDD1

Transmit Data Delay After Serial Clock Falling Edge

9.9

ns

tSRCTDH1

Transmit Data Hold After Serial Clock Falling Edge

1

ns

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG input

can be either CLKIN or any of the DAI pins.