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ADSP1802 Datasheet(PDF) 18 Page - Analog Devices |
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ADSP1802 Datasheet(HTML) 18 Page - Analog Devices |
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18 / 34 page  Data Sheet ADSP1802 SPECIFICATIONS analog.com Rev. D | 18 of 34 Table 31. SPI Interface Protocol—Subordinate Switching and Timing Specifications (Continued) Parameter Description Min Max Unit tSPICLKS Serial Clock Cycle 4 × tPCLK – 2 ns tSPICHS Serial Clock High Period 2 × tPCLK – 2 ns tSPICLS Serial Clock Low Period 2 × tPCLK – 2 ns tSDSCO SPIDS Assertion to First SPICLK Edge, CPHASE = 0, CPHASE = 1 2 × tPCLK ns tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × tPCLK ns tSSPIDS Data Input Valid to SPICLK edge (Data Input Setup Time) 2 ns tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid 2 ns tSDPPW SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × tPCLK ns SWITCHING CHARACTERISTICS ns tDSOE SPIDS Assertion to Data Out Active 0 7.5 ns tDSOE1 SPIDS Assertion to Data Out Active (SPI2) 0 7.5 ns tDSDHI SPIDS Deassertion to Data High Impedance 0 10.5 ns tDSDHI1 SPIDS Deassertion to Data High Impedance (SPI2) 0 10.5 ns tDDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Delay Time) 9.5 ns tHDSPIDS SPICLK Edge to Data Out Valid (Data Out Hold Time) 2 × tPCLK ns tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × tPCLK ns 1 The timing for these parameters applies when the SPI is routed through the signal routing unit. Figure 28. SPI Subordinate Timing Joint Test Action Group (JTAG) Test Access Port and Emulation Table 32. JTAG Test Access Port and Emulation Parameter Description Min Max Unit TIMING REQUIREMENTS tTCK TCK Period 20 ns tSTAP TDI, TMS Setup Before TCK High 5 ns tHTAP TDI, TMS Hold After TCK High 6 ns tSSYS1 System Inputs Setup Before TCK High 7 ns tHSYS1 System Inputs Hold After TCK High 18 ns tTRSTW TRST Pulse Width 4 × tCK ns SWITCHING CHARACTERISTICS tDTDO TDO Delay from TCK Low 10 ns |
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