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ADP5585ACPZ-00-R7 Datasheet(PDF) 14 Page - Analog Devices |
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ADP5585ACPZ-00-R7 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 40 page  ADP5585 Data Sheet Rev. C | Page 14 of 40 RESET BLOCKS ADP5585 features two reset blocks that can generate reset con- ditions if certain events are detected simultaneously. Up to three reset trigger events can be programmed for RESET1. Up to two reset trigger events can be programmed for RESET2. The event scan control blocks monitor whether these events are present for the duration of RESET_TRIG_TIME[2:0] (Register 0x2E, Bits[4:2]). If they are, reset-initiate signals are sent to the reset generator blocks. The generated reset signal pulse width is programmable. RESET_PULSE_WIDTH[1:0] RESET_TRIG_TIME[2:0] RESET1_EVENT_A[7:0] RESET1_EVENT_B[7:0] RESET1_EVENT_C[7:0] KEY SCAN CONTROL RST_PASSTHRU_EN RST (R4) RESET1 GPI SCAN CONTROL LOGIC BLOCK CONTROL RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] (C4) RESET2 RESET1_ INITIATE RESET2_ INITIATE RESET GEN 2 RESET GEN 1 Figure 21. Reset Blocks The Reset 1 signal uses the R4 I/O pin as its output. A pass through mode allows the main RST pin to be output on the R4 pin also. The Reset 2 signal uses the C4 I/O pin as its output. The reset generation signals are useful in situations where the system processor has locked up and the system is unresponsive to input events. The user can press one of the reset event combi- nations and initiate a system wide reset. This alleviates the need for removing the battery from the system and doing a hard reset. It is not recommended to use the immediate trigger time (see Table 54) because this setting may cause false triggering. Interrupts The INT pin can be asserted low if any of the internal interrupt sources is active. The user can select which internal interrupts interact with the external interrupt pin in Register 0x3C (refer to Table 68). Register 0x3B allows the user to choose whether the external interrupt pin remains asserted, or deasserts for 50 µs, then reasserts, in the case that there are multiple internal interrupts asserted and one is cleared (refer to Table 67). EVENT_INT EVENT_IEN INT DRIVE INT INT_CFG GPI_INT GPI_IEN LOGIC_INT LOGIC_IEN OVRFLOW_INT OVRFLOW_IEN Figure 22. Asserting INT Low |
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