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ADP5585ACPZ-00-R7 Datasheet(PDF) 13 Page - Analog Devices |
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ADP5585ACPZ-00-R7 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 40 page  Data Sheet ADP5585 Rev. C | Page 13 of 40 GPI EVENT KEY EVENT LOGIC EVENT (R1) LA LC LB LA_INV D CLR Q SET LB_INV LC_INV FF_SET FF_CLR R3_EXTEND_CFG[1:0] LOGIC_SEL[2:0] LY_INV (R2) (R3) LOGIC BLOCK LY (R0) LOGIC_INT LOGIC_INT_LEVEL LOGIC_EVENT_EN OVRFLOW_INT EVENT_INT RESET_TRIG_TIME[2:0] RESET1_EVENT_A[7:0] RESET1_EVENT_B[7:0] RESET1_EVENT_C[7:0] RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] FIFO EC[4:0] LOGIC EVENT/INT GENERATOR I2C BUSY FIFO UPDATE Figure 18. Logic Block Overview PWM BLOCK The ADP5585 features a PWM generator whose output can be configured to drive out on the R3 I/O pin. PWM on/off times are programmed via four 8-bit registers (see Figure 20). Each bit of the on or off time represents 1 µs. The highest frequency obtainable from the PWM is performed by setting the least significant bit of both the on and off time bit patterns, resulting in a 500 kHz signal with a 50% duty cycle. The PWM block provides support for continuous PWM mode as well as a one-shot mode (see Table 59). Additionally, an external signal can be AND’ed with the internal PWM signal. This option can be selected by writing a 1 to PWM_IN_AND (PWM_CFG[2]). The input to the external AND is the C3 I/O pin. C3 should be set to GPI. Note that the debounce for C3 results in a delay of the AND’ing, and can be turned on or off using Register 0x21. Newly programmed values are not latched until the final byte, PWM_ONT_HIGH_BYTE (Register 0x32, Bits[7:0]), is written. LA_INV MUX 000 001 SEL[2:0] OUT 010 011 100 101 110 111 SEL OUT 0 1 GND AND OR XOR FF IN_LA IN_LB IN_LC LA LA LA IN_LA SEL OUT 0 1 AND IN_LA IN_LB IN_LC R3_EXTEND_CFG[1:0] = 01 LOGIC_SEL[2:0] LY_INV SEL OUT 0 1 LY LY LY LB_INV SEL OUT 0 1 LB LB LB IN_LB LC_INV SEL OUT 0 1 LC LC LC IN_LC FF_SET FF_CLR SEL OUT 0 1 OR IN_LA IN_LB IN_LC AND AND OR OR SEL OUT 0 1 XOR IN_LA IN_LB IN_LC IN_LA IN_LB IN_LC XOR XOR D CLR Q SET 0 1 SEL OUT FF Figure 19. Logic Block (C3) PWM_IN OFF TIME[15:0] PWM_EN PWM_IN_AND PWM_OFFT_LOW_BYTE[7:0] PWM_MODE PWM_OFFT_HIGH_BYTE[7:0] PWM_ONT_LOW_BYTE[7:0] PWM_ONT_HIGH_BYTE[7:0] ON TIME[15:0] SEL OUT 0 1 AND PWM GENERATOR (R3) PWM_OUT Figure 20. PWM Block Diagram |
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