ADP5585ACPZ-00-R7 datasheet(35/40 Pages) AD

Part #	ADP5585ACPZ-00-R7

Description	Keypad Decoder and I/O Expansion

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Manufacturer	AD [Analog Devices]

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Data Sheet

ADP5585

Rev. C | Page 35 of 40

Bit(s)

Bit Name

Access

Description

5

R4_ EXTEND_CFG

Read/write

0 = R4 remains configured as GPIO 5.

1 = R4 reconfigured as RESET1 output.

4

N/A

Reserved.

3 to 2

R3_EXTEND_CFG[1:0]

Read/write

00 = R3 remains configured as GPIO 4.

01 = R3 reconfigured as LC input for the logic block.

10 = R3 reconfigured as PWM_OUT output from PWM block.

11 = unused.

1

N/A

Reserved.

0

R0_ EXTEND_CFG

Read/write

0 = R0 remains configured as GPIO 1.

1 = R0 reconfigured as LY output from the logic block.

GENERAL_CFG Register 0x3B

Table 67. GENERAL_CFG Bit Descriptions

Bit(s)

Bit Name

Access

Description

7

OSC_EN

Read/write

0 = disable internal 1 MHz oscillator.

1 = enable internal 1 MHz oscillator.

6

to 5

OSC_FREQ[1:0]

Read/write

Sets the input clock frequency fed from the base 1 MHz oscillator to the digital

core. Slower frequencies result in less quiescent current, but key and GPI scan

times increase.

00 = 50 kHz.

01 = 100 kHz.

10 = 200 kHz.

11 = 500 kHz.

4

to 2

N/A

Reserved.

1

INT_CFG

Read/write

Configure the behavior of the INT pin if the user tries to clear it while an interrupt

is pending.

0 = INT pin remains asserted if an interrupt is pending.

1 = INT pin deasserts for 50 µs and reasserts if an interrupt is pending.

0

RST_CFG

R/W

Configure the response ADP5585 has to the RST pin.

0 = ADP5585 resets if RST is low.

1 = ADP5585 does not reset if RST is low.

INT_EN Register 0x3C

Table 68. INT_EN Bit Descriptions

Bit(s)

Bit Name

Access

Description

7 to 5

N/A

Reserved.

4

LOGIC_IEN

Read/write

0 = Logic 1 interrupt is disabled.

1 = assert the INT pin if LOGIC_INT is set.

3

N/A

Reserved.

2

OVRFLOW_IEN

Read/write

0 = overflow interrupt is disabled.

1 = assert the INT pin if OVRFLOW_INT is set.

1

GPI_IEN

Read/write

0 = GPI interrupt is disabled.

1 = assert the INT pin if GPI_INT is set.

0

EVENT_IEN

Read/write

0 = event interrupt is disabled.

1 = assert the INT pin if EVENT_INT is set.

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