R5F5630ECDFB datasheet(150/165 Pages) RENESAS

150 / 165 page

R01DS0060EJ0100 Rev.1.00

Page 150 of 168

Sep 13, 2011

RX630 Group

5. Electrical Characteristics

5.9

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Note: • The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1,

and Vdet2 for the POR/ LVD.

Figure 5.40

Power-on Reset Timing

Table 5.26

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0

VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Voltage detection

level

Power-on reset

(POR)

Low power

consumption

function disabled

VPOR

2.5

2.6

2.7

Figure 5.40

Low power

consumption

function enabled

2.0

2.35

2.7

Voltage detection circuit (LVD0)

Vdet0

2.7

2.80

2.9

Figure 5.41

Voltage detection circuit (LVD1)

Vdet1_A

2.75

2.95

3.15

Voltage detection circuit (LVD2)

Vdet2_A

2.75

2.95

3.15

Internal reset time

Power-on reset time

tPOR

—

4.6

—

Figure 5.40

LVD0 reset time

tLVD0

—

4.6

—

Figure 5.41

LVD1 reset time

tLVD1

—

0.9

—

Figure 5.42

LVD2 reset time

tLVD2

—

0.9

—

Figure 5.43

Minimum VCC down time

tVOFF

200

—

µs

Figure 5.40 and

Figure 5.41

Response delay time

tdet

—

200

µs

Figure 5.40 to

Figure 5.43

LVD operation stabilization time (after LVD is enabled)

Td(E-A)

—

µs

Figure 5.42 and

Figure 5.43

Hysteresis width (LVD1 and LVD2)

V LVH

—80

—

Internal reset signal

(active-low)

VCC

tVOFF

tdet

tPOR

tdet

tPOR

tdet

VPOR

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