PRELIMINARY
PSoC®3: CY8C38 Family Data Sheet
Document Number: 001-11729 Rev. *I
Page 26 of 100
Figure 6-3. Power Mode Transitions
6.2.1.1
Active Mode
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
6.2.1.2
Alternate Active Mode
Alternate Active mode is very similar to Active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and Flash, and run peripherals at full speed.
Table 6-2. Power Modes
Power Modes
Description
Entry Condition Wakeup Source
Active Clocks
Regulator
Active
Primary mode of operation, all
peripherals available (program-
mable)
Wakeup, reset,
manual register
entry
Any interrupt
Any (program-
mable)
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
Alternate
Active
Similar to Active mode, and is
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to turn off the
CPU and Flash, and run periph-
erals at full speed
Manual register
entry
Any interrupt
Any (program-
mable)
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
Sleep
All subsystems automatically
disabled
Manual register
entry
PICU,
comparator, I2C,
RTC, CTW,
XRES_N, WDR,
PPOR, HBR
ILO/ECO32K
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Hibernate
All subsystems automatically
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
Manual register
entry
PICU, XRES_N,
HBR
Only hibernate regulator
active.
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup
Time
Power
(typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Wakeup Sources
Reset Sources
Active
-
1.2 mA[5] Yes
All
All
All
-
All
Alternate
Active
-TBD
User
defined
All
All
All
-
All
Sleep
<12 µs
1 µA
No
I2C
Comparator
ILO/kHzECO
PICU, comparator,
I2C, RTC, CTW
XRES, LVD,
WDR
Hibernate <100 µs
200 nA
No
None
None
None
PICU
XRES, HRES
Note
5. IMO 6 MHz, CPU 6 MHz, all peripherals disabled.
Active
Alternate
Active
Hibernate
Sleep
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