92 / 100 page
PRELIMINARY
PSoC®3: CY8C38 Family Data Sheet
Document Number: 001-11729 Rev. *I
Page 92 of 100
11.9.5 External Clock Reference
11.9.6 Phase-Locked Loop
Table 11-82. External Clock Reference AC Specifications[9]
Parameter
Description
Conditions
Min
Typ
Max
Units
External frequency range
0
-
33
MHz
Input duty cycle range
Measured at Vddio/2
30
50
70
%
Input edge rate
Vil to Vih
0.1
-
-
V/ns
Table 11-83. PLL DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Idd
PLL operating current
FREF = 3 MHz, FVCO=66 MHz
-
1920
-
µA
FREF = 3 MHz, FVCO=24 MHz
-
560
-
µA
Table 11-84. PLL AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Fpllinpre
PLL prescaler input frequency
1
-
48
MHz
Fpllin
PLL input frequency
1
-
3
MHz
Fpllout
PLL output frequency
24
-
67
MHz
Lock time at startup
-
-
250
µs
Jperiod-rms Jitter (rms)[9]
--
250
ps
PLL output duty cycle
All PLL output frequencies
45
-
55
%
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