84 / 100 page
PRELIMINARY
PSoC®3: CY8C38 Family Data Sheet
Document Number: 001-11729 Rev. *I
Page 84 of 100
11.7.5 External Memory Interface
Figure 11-2. Asynchronous Read Cycle Timing
Table 11-63. Asynchronous Read Cycle Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
T
EMIF Clock period
30.3
-
-
ns
Tcel
EM_CEn low time
2*T-1
-
2*T+2
ns
Taddrv
EM_CEn low to EM_Addr valid
-
-
5
ns
Taddrh
Address hold time after EM_OEn high
2
-
-
ns
Toev
EM_CEn low to EM_OEn low
-5
-
5
ns
Toel
EM_OEn low time
2*T-1
-
2*T+2
ns
Toeh
EM_OEn high to EM_CEn high hold time
-5
-
5
ns
Tdoesu
Data to EM_OEn high setup time
T+20
-
-
ns
Tdcesu
Data to EM_CEn high setup time
T+20
-
-
ns
Tdoeh
Data hold time after EM_OEn high
3
-
-
ns
Tdceh
Data hold time after EM_CEn high
3
-
-
ns
EM_Addr
EM_CEn
EM_OEn
EM_Data
EM_WEn
Address
Data
Tcel
Taddrv
Taddrh
Toev
Toel
Toeh
Tdcesu
Tdoesu
Tdceh
Tdoeh
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