PRELIMINARY
PSoC®3: CY8C38 Family Data Sheet
Document Number: 001-11729 Rev. *I
Page 76 of 100
11.5.11 Programmable Gain Amplifier
The PGA is created using a SC/CT Analog Block, see the PGA component data sheet in PSoC Creator for full AC/DC specifications,
and APIs and example code.
Table 11-35. PGA DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Vos
Input offset voltage[9]
--
10
mV
DeltaV/DeltaTa Input offset voltage drift[9]
-
±30
-
µV/°C
Output current source capability[9]
Drive setting 3, Vdda = 1.71V
-
-
250
µA
PSRR
Power supply rejection ratio[9]
100 kHz
69
-
-
dB
1 MHz
38
-
-
dB
Zin
Input impedance[9]
For non inverting inputs
35
-
-
M
Ω
Gain Error[9]
Non inverting mode, reference = Vssa
Ge1
Gain = 1
Rin of 40K
-
-
±
0.15
%
Ge2
Gain = 2
Rin of 40K
-
-
±
1%
Ge4
Gain = 4
Rin of 40K
-
-
±
1.03
%
Ge8
Gain = 8
Rin of 40K
-
-
±
1.23
%
Ge16
Gain = 16
Rin of 40K
-
-
±
2.5
%
Ge32
Gain = 32
Rin of 40K
-
-
±
5%
Ge50
Gain = 50
Rin of 40K
-
-
±
5%
Vonl
DC output non linearity G = 1[9]
-
-
0.01
% of FSR
Voh, Vol
Output voltage swing
Vssa +
0.15
-
Vdda -
0.15
V
Quiescent current[9]
-
-
1.65
mA
Table 11-36. PGA AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
-3 db Bandwidth[9]
BW1
Gain = 1
Noninverting mode, 300 mV
≤ Vin
≤ Vdda - 1.2V, Cl ≤ 25 pF
7-
-
MHz
BW24
Gain = 24
Noninverting mode, 300 mV
≤ Vin
≤ Vdda - 1.2V, Cl ≤ 25 pF
360
-
-
kHz
BW48
Gain = 48
Noninverting mode, 300 mV
≤ Vin
≤ Vdda - 1.2V, Cl ≤ 25 pF
215
-
-
kHz
Slew Rate[9]
SR1
Gain = 1
Vdda = 1.71V 5% to 90% FS output
3
-
-
V/µs
SR24
Gain = 24
RC limited
0.5
-
-
V/µs
SR48
Gain = 48
RC limited
0.5
-
-
V/µs
Input Noise Voltage Density[9]
eni1
Gain = 1
10 kHz
-
38
-
nV/sqrtHz
eni24
Gain = 24
10 kHz
-
38
-
nV/sqrtHz
eni48
Gain = 48
10 kHz
-
38
-
nV/sqrtHz
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