R8CSLASH13 datasheet(184/224 Pages) RENESAS

184 / 224 page

R8C/13 Group

Rev.1.20

Jan 27, 2006

page 173 of 205

REJ09B0111-0120

Figure 17.7 Setting and Resetting of EW1 Mode

Program in ROM

EW1 mode operation procedure

NOTES:

1. To set the FMR01 bit to “1”, write

“0” and then “1” in succession.

Make sure no interrupts will occur

before writing “1” after writing “0”.

Set the FMR01 bit by writing “0” and then “1” (CPU

rewrite mode enabled)(1)

Set the FMR11 bit by writing “0” and then “1” (EW1

mode)

Execute software commands

Write “0” to the FMR01 bit

(CPU rewrite mode disabled)

Execute the Read Array command(3)

Set CM0 and CM1 registers(1)

Execute software commands

Jump to the rewrite control program which has been

transferred to any area other than the flash memory

(The subsequent processing is executed by the

rewrite control program in any area other than the

flash memory)

Transfer a CPU rewrite mode based rewrite control

program to any area other than the flash memory

Write “0” to the FMR01 bit

(CPU rewrite mode disabled)

Set the FMR01 bit by writing “0” and then “1”

(CPU rewrite mode enabled)(2)

EW0 mode operation procedure

Rewrite control program

Jump to a specified address in the flash memory

NOTES:

1. Select 5 MHz or less for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register.

2. To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no interrupts will occur before writing “1” after writing “0”.

Write to the FMR01 bit from a program in other than the flash memory.

3. Disables the CPU rewrite mode after executing the Read Array command.

Figure 17.6 Setting and Resetting of EW0 Mode

Figures 17.6 and 17.7 show the setting and resetting of EW0 mode and EW1 mode, respectively.

17.4 CPU Rewrite Mode

During Erase

Erase

Starts

FMR00

FMR46

Erase

Suspends

Erase

Starts

Check that the FMR00 bit is

set to “0”, and that the erase

operation has not ended.

Check the status,

and that the program

ends normally.

Erase

Ends

During Erase

Figures 17.5 shows the timing on suspend operation.

Figure 17.5 Timing on Suspend Operation

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