R8CSLASH13 datasheet(180/224 Pages) RENESAS

180 / 224 page

R8C/13 Group

Rev.1.20

Jan 27, 2006

page 169 of 205

REJ09B0111-0120

17.4.1 EW0 Mode

The microcomputer is placed in CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1”

(CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's

FMR11 bit = 0, EW0 mode is selected.

Use software commands to control program and erase operations. Read the FMR0 register or status

When moving to an erase-suspend during auto-erase, set the FMR40 bit to “1” (erase-suspend en-

abled ) and the FMR41 bit to “1” (erase-suspend requested). Wait for td(SR-ES) and make sure that

the FMR46 bit is set to “1” (enables reading) before accessing the user ROM space. The auto-erase

operation resumes by setting the FMR41 bit to “0” (erase restart).

17.4.2 EW1 Mode

EW1 mode is selected by setting FMR11 bit to “1” (EW1 mode) after setting the FMR01 bit to “1” (CPU

rewrite mode enabled).

Read the FMR0 register to check the status of program or erase operation at completion. Avoid ex-

ecuting software commands of Read Status register in EW1 mode.

To enable the erase-suspend function, the Block Erase command should be executed after setting the

FMR40 bit to “1” (erase-suspend enabled). An interrupt to request an erase-suspend must be in en-

abled state. After passing td(SR-ES) since the block erase command is executed, an interrupt request

can be acknowledged.

When an interrupt request is generated, FMR41 bit is automatically set to “1” (erase-suspend re-

quested) and the auto-erase operation is halted. If the auto-erase operation is not completed (FMR00

bit is “0”) when the interrupt routine is ended, the Block Erase command should be executed again by

settingthe FMR41 bit to “0” (erase restart).

17.4 CPU Rewrite Mode

R8C/13 Datasheet(PDF) 180 Page - Renesas Technology Corp